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LTC2483 16-Bit ADC with Easy Drive Input Current Cancellation and I2C Interface
FEATURES

DESCRIPTIO
Easy Drive Technology Enables Rail-to-Rail Inputs with Zero Differential Input Current Directly Digitizes High Impedance Sensors with Full Accuracy 600nV RMS Noise, Independent of VREF GND to VCC Input/Reference Common Mode Range 2-Wire I2C Interface Simultaneous 50Hz/60Hz Rejection 2ppm (0.25LSB) INL, No Missing Codes 1ppm Offset and 15ppm Full-Scale Error No Latency: Digital Filter Settles in a Single Cycle Single Supply 2.7V to 5.5V Operation Internal Oscillator Six Addresses Available and One Global Address for Synchronization Available in a Tiny (3mm x 3mm) 10-Lead DFN Package
The LTC(R)2483 combines a 16-bit plus sign No Latency TM analog-to-digital converter with patented Easy DriveTM technology and I2C digital interface. The patented sampling scheme eliminates dynamic input current errors and the shortcomings of on-chip buffering through automatic cancellation of differential input current. This allows large external source impedances and input signals, with rail-torail input range to be directly digitized while maintaining exceptional DC accuracy. The LTC2483 allows a wide common mode input range (0V to VCC) independent of the reference voltage. The reference can be as low as 100mV or can be tied directly to VCC. The noise level is 600nV RMS independent of VREF. This allows direct digitization of low level signals with 16bit accuracy. The LTC2483 includes an on-chip trimmed oscillator, eliminating the need for external crystals or oscillators and provides 87dB rejection of 50Hz and 60Hz line frequency noise. Absolute accuracy and low drift are automatically maintained through continuous, transparent, offset and full-scale calibration.
, LTC and LT are registered trademarks of Linear Technology Corporation. No Latency and Easy Drive are trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Patent Pending.
APPLICATIO S

Direct Sensor Digitizer Weight Scales Direct Temperature Measurement Strain Gauge Transducers Instrumentation Industrial Process Control DVMs and Meters
TYPICAL APPLICATIO
VCC
+FS Error vs RSOURCE at IN+ and IN-
80 VCC = 5V 60 VREF = 5V VIN+ = 3.75V - 40 VIN = 1.25V FO = GND 20 TA = 25C CIN = 1F 0 -20 -40 -60 -80 1 10 100 1k RSOURCE () 10k 100k
2483 TA02
10k SENSE 10k
IDIFF = 0 1F
VIN+
REF+ LTC2483
VCC
SCL SDA CA0/F0 CA1
2483 TA01
2-WIRE I2C INTERFACE 6 ADDRESSES
VIN- GND
REF-
+FS ERROR (ppm)
1F
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LTC2483
ABSOLUTE
(Notes 1, 2)
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RATI GS
PACKAGE/ORDER I FOR ATIO
TOP VIEW REF+ 1 VCC 2 REF - 3 IN+ 4 IN- 5 11 10 CA0/F0 9 CA1 8 GND 7 SDA 6 SCL
Supply Voltage (VCC) to GND ...................... - 0.3V to 6V Analog Input Voltage to GND ....... - 0.3V to (VCC + 0.3V) Reference Input Voltage to GND .. - 0.3V to (VCC + 0.3V) Digital Input Voltage to GND ........ - 0.3V to (VCC + 0.3V) Digital Output Voltage to GND ..... - 0.3V to (VCC + 0.3V) Operating Temperature Range LTC2483C ................................................... 0C to 70C LTC2483I ................................................ - 40C to 85C Storage Temperature Range ................ - 65C to 125C
DD PACKAGE 10-LEAD (3mm x 3mm) PLASTIC DFN
TJMAX = 125C, JA = 43C/ W EXPOSED PAD (PIN 11) IS GND MUST BE SOLDERED TO PCB
ORDER PART NUMBER LTC2483CDD LTC2483IDD
DD PART MARKING* LBSR
Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: http://www.linear.com/leadfree/ Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
ELECTRICAL CHARACTERISTICS
PARAMETER Resolution (No Missing Codes) Integral Nonlinearity Offset Error Offset Error Drift Positive Full-Scale Error Positive Full-Scale Error Drift Negative Full-Scale Error Negative Full-Scale Error Drift Total Unadjusted Error CONDITIONS
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Notes 3, 4)
MIN

TYP 2 1 0.5 10
MAX 10 2.5 25
UNITS Bits ppm of VREF ppm of VREF V nV/C ppm of VREF ppm of VREF/C
0.1 VREF VCC, -FS VIN +FS (Note 5) 5V VCC 5.5V, VREF = 5V, VIN(CM) = 2.5V (Note 6) 2.7V VCC 5.5V, VREF = 2.5V, VIN(CM) = 1.25V (Note 6) 2.5V VREF VCC, GND IN+ = IN- VCC (Note 13) 2.5V VREF VCC, GND IN+ = IN- VCC 2.5V VREF VCC, IN+ = 0.75VREF, IN- = 0.25VREF 2.5V VREF VCC, IN+ = 0.75VREF, IN- = 0.25VREF 2.5V VREF VCC, IN- = 0.75VREF, IN+ = 0.25VREF 2.5V VREF VCC , IN- = 0.75VREF, IN+ = 0.25VREF
16
0.1
25 0.1 15 15 15 0.6
ppm of VREF ppm of VREF/C ppm of VREF ppm of VREF ppm of VREF VRMS
5V VCC 5.5V, VREF = 2.5V, VIN(CM) = 1.25V (Note 6) 5V VCC 5.5V, VREF = 5V, VIN(CM) = 2.5V (Note 6) 2.7V VCC 5.5V, VREF = 2.5V, VIN(CM) = 1.25V (Note 6) 5V VCC 5.5V, VREF = 5V, GND IN- = IN+ VCC (Note 12)
Output Noise
2
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LTC2483
CO VERTER CHARACTERISTICS
PARAMETER Input Common Mode Rejection DC Input Common Mode Rejection 50Hz 2% Input Common Mode Rejection 60Hz 2% Input Normal Mode Rejection 50Hz 2% Input Normal Mode Rejection 60Hz 2% Input Normal Mode Rejection 50Hz/60Hz 2% Reference Common Mode Rejection DC Power Supply Rejection DC Power Supply Rejection, 50Hz 2% Power Supply Rejection, 60Hz 2% CONDITIONS
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Notes 3, 4)
MIN

A ALOG I PUT A D REFERE CE The denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25C. (Note 3)
SYMBOL IN+ IN- FS LSB VIN VREF CS (IN+) CS (IN-) CS (VREF) IDC_LEAK (IN+) IDC_LEAK (IN-) IDC_LEAK (VREF) PARAMETER Absolute/Common Mode IN+ Voltage Absolute/Common Mode IN- Voltage Full Scale of the Differential Input (IN+ - IN-)

Least Significant Bit of the Output Code Input Differential Voltage Range (IN+ - IN-) Reference Voltage Range (REF+ IN+ Sampling Capacitance IN- Sampling Capacitance VREF Sampling Capacitance IN+ DC Leakage Current DC Leakage Current Sleep Mode, IN+ = GND Sleep Mode, IN- = GND Sleep Mode, VREF = VCC - REF-)
IN- DC Leakage Current REF+, REF-
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TYP
MAX
UNITS dB dB dB
2.5V VREF VCC, GND IN- = IN+ VCC (Note 5) 2.5V VREF VCC, GND IN- = IN+ VCC (Note 5)
140 140 140 110 110 87 120 140 120 120 120 120 120
2.5V VREF VCC, GND IN- = IN+ VCC (Note 5) 2.5V VREF VCC, GND IN- = IN+ VCC (Notes 5, 7) 2.5V VREF VCC, GND IN- = IN+ VCC (Notes 5, 8) 2.5V VREF VCC, GND IN- = IN+ VCC (Notes 5, 9) 2.5V VREF VCC, GND IN- = IN+ VCC (Note 5) VREF = 2.5V, IN- = IN+ = GND VREF VREF = 2.5V, IN- = 2.5V, IN- = IN+ = IN+ = GND (Notes 7, 9) = GND (Notes 8, 9)
dB dB dB dB dB dB dB
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CONDITIONS
MIN GND - 0.3V GND - 0.3V 0.5VREF FS/216 -FS 0.1
TYP
MAX VCC + 0.3V VCC + 0.3V
UNITS V V V
+FS VCC 11 11 11
V V pF pF pF

-10 -10 -100
1 1 1
10 10 100
nA nA nA
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LTC2483 I2C DIGITAL I PUTS A D DIGITAL OUTPUTS
SYMBOL VIH VIL VIL(CA1) VIH(CA0/F0,CA1) RINH RINL RINF II VHYS VOL tOF tSP IIN CI CB CCAX VIH(EXT,OSC) VIL(EXT,OSC) PARAMETER High Level Input Voltage Low Level Input Voltage Low Level Input Voltage for Address Pin High Level Input Voltage for Address Pins Resistance from CA0/F0,CA1 to VCC to Set Chip Address Bit to 1 Resistance from CA1 to GND to Set Chip Address Bit to 0 Resistance from CA0/F0, CA1 to VCC or GND to Set Chip Address Bit to Float Digital Input Current Hysteresis of Schmitt Trigger Inputs Low Level Output Voltage SDA Output Fall Time from VIHMIN to VILMAX Input Spike Suppression Input Leakage Capacitance for Each I/O Pin Capacitance Load for Each Bus Line External Capacitive Load on Chip Address Pins (CA0/F0,CA1) for Valid Float High Level CA0/F0 External Oscillator Low Level CA0/F0 External Oscillator 2.7V VCC < 5.5V 2.7V VCC < 5.5V 0.1VCC VIN VCC (Note 5) I = 3mA
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 3)
CONDITIONS

POWER REQUIRE E TS
SYMBOL VCC ICC PARAMETER Supply Voltage Supply Current
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 3)
CONDITIONS
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MIN 0.7VCC
TYP
MAX 0.3VCC 0.05VCC
UNITS V V V V k k M
0.95VCC 10 10 2 -10 0.05VCC 0.4 20+0.1CB 250 50 1 10 400 10 VCC - 0.5V 0.5 10
A V V ns ns A pF pF pF V V
Bus Load CB 10pF to 400pF (Note 14)

MIN 2.7

TYP 160 1
MAX 5.5 250 2
UNITS V A A
Conversion Mode (Note 11) Sleep Mode (Note 11)
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LTC2483
TI I G CHARACTERISTICS
SYMBOL fEOSC tHEO tLEO tCONV_1 PARAMETER External Oscillator Frequency Range External Oscillator High Period External Oscillator Low Period Conversion Time
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 3)
CONDITIONS

The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Notes 3, 15)
SYMBOL fSCL tHD(SDA) tLOW tHIGH tSU(STA) tHD(DAT) tSU(DAT) tr tf tSU(STO) PARAMETER SCL Clock Frequency Hold Time (Repeated) START Condition LOW Period of the SCL Clock Pin HIGH Period of the SCL Clock Pin Set-Up Time for a Repeated START Condition Data Hold Time Data Set-Up Time Rise Time for Both SDA and SCL Signals Fall Time for Both SDA and SCL Signals Set-Up Time for STOP Condition (Note 14) (Note 14) CONDITIONS

I2C TI I G CHARACTERISTICS
Note 1: Absolute Maximum Ratings are those values beyond which the life of the device may be impaired. Note 2: All voltage values are with respect to GND. Note 3: VCC = 2.7V to 5.5V unless otherwise specified. VREF = REF+ - REF-, VREFCM = (REF+ + REF-)/2, FS = 0.5VREF; VIN = IN+ - IN-, VINCM = (IN+ + IN-)/2. Note 4: Use internal conversion clock or external conversion clock source with fEOSC = 307.2kHz unless otherwise specified. Note 5: Guaranteed by design, not subject to test. Note 6: Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. Note 7: 50Hz fEOSC = 256kHz 2% (external oscillator).
UW
UW
MIN 10 0.125 0.125 144.1
TYP
MAX 4000 100 100
UNITS kHz s s ms ms
Simultaneous 50Hz/60Hz External Oscillator (Note 10)

146.9 149.9 41036/fEOSC
MIN 0 0.6 1.3 0.6 0.6 0 100 20+0.1CB 20+0.1CB 0.6
TYP
MAX 400
UNITS kHz s s s s
0.9 300 300
s ns ns ns s
Note 8: 60Hz fEOSC = 307.2kHz 2% (external oscillator). Note 9: Simultaneous 50Hz/60Hz (internal oscillator) or fEOSC = 280kHz 2% (external oscillator). Note 10: The external oscillator is connected to the CA0/F0 pin. The external oscillator frequency, fEOSC, is expressed in kHz. Note 11: The converter uses the internal oscillator. Note 12: The output noise includes the contribution of the internal calibration operations. Note 13: Guaranteed by design and test correlation. Note 14: CB = capacitance of one bus line in pF. Note 15: All values refer to VIH(MIN) and VIL(MAX) levels.
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LTC2483 TYPICAL PERFOR A CE CHARACTERISTICS
Integral Nonlinearity (VCC = 5V, VREF = 5V)
3 2 VCC = 5V VREF = 5V VIN(CM) = 2.5V -45C
INL (ppm OF VREF)
1 0
INL (ppm OF VREF)
INL (ppm OF VREF)
25C
85C -1 -2 -3 -2.5 -2 -1.5 -1 -0.5 0 0.5 1 1.5 INPUT VOLTAGE (V)
Total Unadjusted Error (VCC = 5V, VREF = 5V)
12 8
TUE (ppm OF VREF)
VCC = 5V VREF = 5V VIN(CM) = 2.5V 25C
85C
TUE (ppm OF VREF)
TUE (ppm OF VREF)
4 0 -4 -8 -12 -2.5 -2 -1.5 -1 -0.5 0 0.5 1 1.5 INPUT VOLTAGE (V) -45C
Noise Histogram (6.8sps)
10,000 CONSECUTIVE READINGS 12 RMS = 0.60V VCC = 5V AVERAGE = -0.69V VREF = 5V 10 VIN = 0V TA = 25C 8 6 4 2 0 -3 -2.4 -1.8 -1.2 -0.6 0 0.6 OUTPUT READING (V) 1.2 1.8 14
14
NUMBER OF READINGS (%)
NUMBER OF READINGS (%)
ADC READING (V)
6
UW
2
2483 G01
Integral Nonlinearity (VCC = 5V, VREF = 2.5V)
3 2 1 -45C, 25C, 90C 0 -1 -2 -3 -1.25 VCC = 5V VREF = 2.5V VIN(CM) = 1.25V
3 2 1
Integral Nonlinearity (VCC = 2.7V, VREF = 2.5V)
VCC = 2.7V VREF = 2.5V VIN(CM) = 1.25V
-45C, 25C, 90C 0 -1 -2 -3 -1.25
2.5
-0.75
-0.25 0.25 0.75 INPUT VOLTAGE (V)
1.25
2483 G02
-0.75
-0.25 0.25 0.75 INPUT VOLTAGE (V)
1.25
2483 G03
Total Unadjusted Error (VCC = 5V, VREF = 2.5V)
12 8 4 0 -4 -8 -12 -1.25 -45C VCC = 5V VREF = 2.5V VIN(CM) = 1.25V 25C 4 0 -4 -8 12 85C 8
Total Unadjusted Error (VCC = 2.7V, VREF = 2.5V)
VCC = 2.7V VREF = 2.5V VIN(CM) = 1.25V 25C 85C
-45C
2
2.5
-0.75
-0.25 0.25 0.75 INPUT VOLTAGE (V)
1.25
2483 G05
-12 -1.25
-0.75
-0.25 0.25 0.75 INPUT VOLTAGE (V)
1.25
2483 G06
2483 G04
Noise Histogram (7.5sps)
10,000 CONSECUTIVE READINGS RMS = 0.59V 12 VCC = 2.7V AVERAGE = -0.19V VREF = 2.5V 10 VIN = 0V TA = 25C 8 6 4 2 0 -3 -2.4 -1.8 -1.2 -0.6 0 0.6 OUTPUT READING (V) 1.2 1.8
Long-Term ADC Readings
5 VCC = 5V, VREF = 5V, VIN = 0V, VIN(CM) = 2.5V 4 TA = 25C, RMS NOISE = 0.60V 3 2 1 0 -1 -2 -3 -4 -5 0 10 30 40 20 TIME (HOURS) 50 60
2483 G09
2483 G07
2483 G08
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LTC2483 TYPICAL PERFOR A CE CHARACTERISTICS
RMS Noise vs Input Differential Voltage
1.0 0.9 VCC = 5V VREF = 5V VIN(CM) = 2.5V TA = 25C
RMS NOISE (V)
RMS NOISE (ppm OF VREF)
0.8 0.7 0.6 0.5 0.4 -2.5 -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 INPUT DIFFERENTIAL VOLTAGE (V)
RMS NOISE (V)
RMS Noise vs VCC
1.0 0.9 RMS NOISE (V) 0.8 0.7 0.6 0.5 0.4 2.7 VREF = 2.5V VIN = 0V VIN(CM) = GND TA = 25C
RMS NOISE (V)
1.0 0.9 0.8 0.7 0.6 0.5 0.4
OFFSET ERROR (ppm OF VREF)
3.1
3.5
3.9 4.3 VCC (V)
4.7
Offset Error vs Temperature
0.3 0.2 0.1 0 VCC = 5V VREF = 5V VIN = 0V VIN(CM) = GND
OFFSET ERROR (ppm OF VREF)
OFFSET ERROR (ppm OF VREF)
0.1 0 -0.1 -0.2
OFFSET ERROR (ppm OF VREF)
-0.1 -0.2
-0.3 -45 -30 -15
0 15 30 45 60 TEMPERATURE (C)
UW
2483 G10
RMS Noise vs VIN(CM)
1.0 0.9 0.8 0.7 0.6 0.5 0.4 VCC = 5V VREF = 5V VIN = 0V VIN(CM) = GND TA = 25C 1.0 0.9 0.8 0.7 0.6 0.5
RMS Noise vs Temperature (TA)
VCC = 5V VREF = 5V VIN = 0V VIN(CM) = GND
2.5
-1
0
1
2
3
4
5
6
2483 G11
0.4 -45 -30 -15
VIN(CM) (V)
0 15 30 45 60 TEMPERATURE (C)
75
90
2483 G12
RMS Noise vs VREF
0.3
VCC = 5V VIN = 0V VIN(CM) = GND TA = 25C
Offset Error vs VIN(CM)
VCC = 5V VREF = 5V VIN = 0V TA = 25C
0.2 0.1 0 -0.1 -0.2 -0.3
5.1
5.5
0
1
2
3 VREF (V)
4
5
2483 G14
-1
0
1
3 2 VIN(CM) (V)
4
5
6
2483 G15
2483 G13
Offset Error vs VCC
0.3 0.2 REF+ = 2.5V REF- = GND VIN = 0V VIN(CM) = GND TA = 25C
0.3 0.2 0.1 0
Offset Error vs VREF
VCC = 5V REF- = GND VIN = 0V VIN(CM) = GND TA = 25C
-0.1 -0.2
75
90
-0.3 2.7
3.1
3.5
3.9 4.3 VCC (V)
4.7
5.1
5.5
-0.3 0 1 2 3 VREF (V) 4 5
2483.G18
2483 G16
2483 G17
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LTC2483 TYPICAL PERFOR A CE CHARACTERISTICS
On-Chip Oscillator Frequency vs Temperature
310
308
FREQUENCY (kHz)
FREQUENCY (kHz)
306
306
REJECTION (dB)
304 VCC = 4.1V VREF = 2.5V VIN = 0V VIN(CM) = GND 0 15 30 45 60 TEMPERATURE (C) 75 90
302
300 -45 -30 -15
PSRR vs Frequency at VCC
0 -20 -40 VCC = 4.1V DC 1.4V VREF = 2.5V IN+ = GND IN- = GND TA = 25C
CONVERSION CURRENT (A)
REJECTION (dB)
REJECTION (dB)
-60 -80 -100 -120 -140 0 20 40 60 80 100 120 140 160 180 200 220 FREQUENCY AT VCC (Hz)
2483 G24
Sleep Mode Current vs Temperature
2.0 1.8
SLEEP MODE CURRENT (A)
1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 -45 -30 -15 0 15 30 45 60 TEMPERATURE (C) 75 90 VCC = 2.7V VCC = 5V
SUPPLY CURRENT (A)
8
UW
2483 G21
On-Chip Oscillator Frequency vs VCC
310 VREF = 2.5V VIN = 0V VIN(CM) = GND
0 -20 -40 -60 -80 -100
PSRR vs Frequency at VCC
VCC = 4.1V DC VREF = 2.5V IN+ = GND IN- = GND TA = 25C
308
304
302
-120 -140
300
2.5
3.0
3.5
4.0 VCC (V)
4.5
5.0
5.5
2483 G22
1
10
10k 100k 1k 100 FREQUENCY AT VCC (Hz)
1M
2483 G23
PSRR vs Frequency at VCC
VCC = 4.1V DC 0.7V VREF = 2.5V -20 IN+ = GND IN- = GND -40 TA = 25C -60 -80 -100 -120 -140 30600 0
Conversion Current vs Temperature
200
180 VCC = 5V 160 VCC = 2.7V
140
120
30650
30750 FREQUENCY AT VCC (Hz)
30700
30800
2483 G25
100 -45 -30 -15
0 15 30 45 60 TEMPERATURE (C)
75
90
2483 G26
Conversion Current vs Output Data Rate
500 450 400 350 300 250 200 150 100 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC)
2483 G28
VREF = VCC IN+ = GND IN- = GND CA0/F0 = EXT OSC TA = 25C
VCC = 5V
VCC = 3V
2483 G27
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LTC2483
PI FU CTIO S
REF+ (Pin 1), REF- (Pin 3): Differential Reference Input. The voltage on these pins can have any value between GND and VCC as long as the reference positive input, REF+, is more positive than the reference negative input, REF -, by at least 0.1V. VCC (Pin 2): Positive Supply Voltage. Bypass to GND (Pin 8) with a 1F tantalum capacitor in parallel with 0.1F ceramic capacitor as close to the part as possible. IN+ (Pin 4), IN- (Pin 5): Differential Analog Input. The voltage on these pins can have any value between GND - 0.3V and VCC + 0.3V. Within these limits the converter bipolar input range (VIN = IN+ - IN-) extends from -0.5 * VREF to 0.5 * VREF. Outside this input range the converter produces unique overrange and underrange output codes. SCL (Pin 6): Serial Clock Pin of the I2C Interface. The LTC2483 can only act as a slave and the SCL pin only accepts external serial clock. Data is shifted out the SDA pin on the falling edges of the SCL clock. SDA (Pin 7): Serial Data Output Line of the I2C Interface. In the transmitter mode (Read), the conversion result is output through the SDA pin. It is an open-drain N-channel driver and therefore an external pull-up resistor or current source to VCC is needed. GND (Pin 8): Ground. Connect this pin to a ground plane through a low impedance connection. CA1 (Pin 9): Chip Address Control Pin. The CA1 pin is configured as a three state (LOW, HIGH, or Floating) address control bit for the device I2C address. CA0/F0 (Pin 10): Chip Address Control Pin/External Clock Input Pin. When no transition is detected on the CA0/F0 pin, it is a two state (HIGH or Floating) address control bit for the device I2C address. When the pin is driven by an external clock signal with a frequency fEOSC of at least 10kHz, the converter uses this signal as its system clock and the fundamental digital filter rejection null is located at a frequency fEOSC/5120 and sets the Chip Address CA0 internally to a HIGH.
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LTC2483
FU CTIO AL BLOCK DIAGRA
1
REF+
4
IN+
IN+
REF+ 3RD ORDER ADC
5
IN
-
IN -
REF -
AUTOCALIBRATION AND CONTROL
REF- 3
10
W
2 VCC
SCL I 2C SERIAL INTERFACE
6
U
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SDA CA1 CA0/F0
7
9
10
GND 8
INTERNAL OSCILLATOR
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LTC2483
APPLICATIO S I FOR ATIO
CONVERTER OPERATION Converter Operation Cycle
The LTC2483 is a low power, analog-to-digital converter with an I2C interface. After power on reset, its operation is made up of three states. The converter operating cycle begins with the conversion, followed by the low power sleep state and ends with the data output (see Figure 1).
POWER ON RESET
CONVERSION
SLEEP
NO
ACKNOWLEDGE
YES
DATA OUTPUT
NO
STOP OR READ 24-BITS YES
2483 F01
Figure 1. LTC2483 State Transition Diagram
Initially, the LTC2483 performs a conversion. Once the conversion is complete, the device enters the sleep state. While in this sleep state, power consumption is reduced by two orders of magnitude. The part remains in the sleep state as long as it is not addressed for a read operation. The conversion result is held indefinitely in a static shift register while the converter is in the sleep state. The device will not acknowledge an external request during the conversion state. After a conversion is finished, the device is ready to accept a read request. Once the
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LTC2483 is addressed for a read operation, the device begins outputting the conversion result under control of the serial clock (SCL). There is no latency in the conversion result. The data output is 24 bits long and contains a 16-bit plus sign conversion result. This result is shifted out on the SDA pin under the control of the SCL. Data is updated on the falling edges of SCL allowing the user to reliably latch data on the rising edge of SCL. A new conversion is initiated at the conclusion of a data read operation (read out all 24 bits). I2C INTERFACE The LTC2483 communicates through an I2C interface. The I2C interface is a 2-wire open-drain interface supporting multiple devices and masters on a single bus. The connected devices can only pull the bus wires LOW and they never drive the bus HIGH. The bus wires are externally connected to a positive supply voltage via a currentsource or pull-up resistor. When the bus is free, both lines are HIGH. Data on the I2C-bus can be transferred at rates of up to 100kbit/s in the Standard-mode and up to 400kbit/s in the Fast-mode. Each device on the I2C bus is recognized by a unique address stored in that device and can operate as either a transmitter or receiver, depending on the function of the device. In addition to transmitters and receivers, devices can also be considered as masters or slaves when performing data transfers. A master is the device which initiates a data transfer on the bus and generates the clock signals to permit that transfer. At the same time any device addressed is considered a slave. The LTC2483 can only be addressed as a slave. Once addressed, it can transmit the last conversion result. Therefore the serial clock line SCL is an input only and the data line SDA is bidirectional (data out/address in). The device supports the Standard-mode and the Fast-mode for data transfer speeds up to 400kbit/s. Figure 2 shows the definition of timing for Fast/Standard-mode devices on the I2C-bus.
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LTC2483
APPLICATIO S I FOR ATIO
The START and STOP Conditions
A START condition is generated by transitioning SDA from HIGH to LOW while SCL is HIGH. The bus is considered to be busy after the START condition. When the data transfer is finished, a STOP condition is generated by transitioning SDA from LOW to HIGH while SCL is HIGH. The bus is free again a certain time after the STOP condition. START and STOP conditions are always generated by the master. When the bus is in use, it stays busy if a repeated START (Sr) is generated instead of a STOP condition. The repeated START (Sr) conditions are functionally identical to the START (S).
SDA tf SCL S tHD;STA tHD;DAT tHIGH tSU;STA Sr tSU;STO P S
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tLOW
tr
tSU;DAT
Figure 2. Definition of Timing for F/S-Mode Devices on the I2C-Bus
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Data Transferring After the START condition, the I2C bus is busy and data transfer is set between a master and a slave. Data is transferred over I2C in groups of nine bits (one byte) followed by an acknowledge bit, therefore each group takes nine SCL cycles. The transmitter releases the SDA line during the acknowledge clock pulse and the receiver issues an Acknowledge (ACK) by pulling SDA LOW or leaves SDA HIGH to indicate a Not Acknowledge (NAK) condition. Change of data state can only happen while SCL is LOW.
tr tHD;STA tSP tr tBUF
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LTC2483
APPLICATIO S I FOR ATIO
LTC2483 Data Format
After a START condition, the master sends a 7-bit address followed by a R/W bit. The bit R/W is 1 for a Read request and 0 for a Write request. If the 7-bit address agrees with an LTC2483's address, that device is selected. When the device is in the conversion state, it does not accept the request and issues a Not-Acknowledge (NAK) by leaving SDA HIGH. A write operation will also generate an NAK signal. If the conversion is complete, it issues an acknowledge (ACK) by pulling SDA LOW. The output register contains the last conversion result. After each conversion is completed, the device automatically enters the sleep state where the supply current is reduced to 1A. When the LTC2483 is addressed for a Read operation, it acknowledges (by pulling SDA LOW) and acts as a transmitter. The master and receiver can read up to three bytes from the LTC2483. After a complete Read operation (3 bytes), the output register is emptied, a new conversion is initiated, and a following Read request in the same output phase will be NAKed. The LTC2483 output data stream is 24 bits long, shifted out on the falling edges of SCL. The first bit is the conversion result sign bit (SIG), see Tables 1 and 2. This bit is HIGH if VIN 0. It is LOW if VIN <0. The second bit is the most significant bit (MSB) of the result. The first two bits (SIG and MSB) can be used to
Table 2. LTC2483 Output Data Format
DIFFERENTIAL INPUT VOLTAGE VIN * VIN* FS** FS** - 1LSB 0.5 * FS** 0.5 * FS** - 1LSB 0 -1LSB - 0.5 * FS** - 0.5 * FS** - 1LSB - FS** VIN* < -FS** BIT 23 SIG 1 1 1 1 1 0 0 0 0 0 BIT 22 MSB 1 0 0 0 0 1 1 1 1 0
*The differential input voltage VIN = IN+ - IN-. **The full-scale voltage FS = 0.5 * VREF.
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indicate over range conditions. If both bits are HIGH, the differential input voltage is above +FS and the following 16 bits are set to LOW to indicate an overrange condition. If both bits are LOW, the input voltage is below -FS and the following 16 bits are set to HIGH to indicate an underrange condition. The function of these two bits is summarized in Table 1. The next 16 bits contain the conversion results in binary two's complement format. The remaining six bits are LOW.
Table 1. LTC2483 Status Bits
INPUT RANGE VIN 0.5 * VREF 0V VIN < 0.5 * VREF -0.5 * VREF VIN < 0V VIN < - 0.5 * VREF BIT 23 SIG 1 1 0 0 BIT 22 MSB 1 0 1 0
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As long as the voltage on the IN+ and IN- pins is maintained within the - 0.3V to (VCC + 0.3V) absolute maximum operating range, a conversion result is generated for any differential input voltage VIN from -FS = -0.5 * VREF to +FS = 0.5 * VREF. For differential input voltages greater than +FS, the conversion result is clamped to the value corresponding to the +FS + 1LSB. For differential input voltages below -FS, the conversion result is clamped to the value corresponding to -FS - 1LSB.
BIT 21 0 1 1 0 0 1 1 0 0 1
BIT 20 0 1 0 1 0 1 0 1 0 1
BIT 19 0 1 0 1 0 1 0 1 0 1
... ... ... ... ... ... ... ... ... ... ...
BIT 6 0 1 0 1 0 1 0 1 0 1
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APPLICATIO S I FOR ATIO
Initiating a New Conversion
When the LTC2483 finishes a conversion, it automatically enters the sleep state. Once in the sleep state, the device is ready for a Read operation. After the device acknowledges a Read request, the device exits the sleep state and enters the data output state. The data output state concludes and the LTC2483 starts a new conversion once a STOP condition is issued by the master or all 24-bits of data are read out of the device. During the data read cycle, a stop command may be issued by the master controller in order to start a new conversion and abort the data transfer. This stop command must be issued during the 9th clock cycle of a byte read when the bus is free (the ACK/NAK cycle). LTC2483 Address The LTC2483 has two address pins, enabling one in 6 possible addresses, as shown in Table 3.
Table 3. LTC2483 Address Assignment
CA1 LOW LOW Floating Floating HIGH HIGH CA0/F0 * HIGH Floating HIGH Floating HIGH Floating Address 001 01 00 001 01 01 001 01 11 010 01 00 010 01 10 010 01 11
* CA0/F0 is treated as HIGH when driven by a valid external clock.
Data Read The data read operation sequence is shown in Figure 5. When the conversion is finished, the device may be addressed for a read operation. At the end of a read operation, a new conversion begins. At the conclusion of the conversion cycle, the next result may be read using the method described above. If the conversion cycle is not concluded and a valid address selects the device, the LTC2483 generates a NAK signal indicating the conversion cycle is in progress.
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Easy Drive Input Current Cancellation The LTC2483 combines a high precision delta-sigma ADC with an automatic differential input current cancellation front end. A proprietary front-end passive sampling network transparently removes the differential input current. This enables external RC networks and high impedance sensors to directly interface to the LTC2483 without external amplifiers. The remaining common mode input current is eliminated by either balancing the differential input impedances or setting the common mode input equal to the common mode reference (see Automatic Input Current Cancellation section). This unique architecture does not require on-chip buffers enabling input signals to swing all the way to ground and up to VCC. Furthermore, the cancellation does not interfere with the transparent offset and full-scale auto-calibration and the absolute accuracy (full scale + offset + linearity) is maintained even with external RC networks. Conversion Clock A major advantage the delta-sigma converter offers over conventional type converters is an on-chip digital filter (commonly implemented as a SINC or Comb filter). For high resolution, low frequency applications, this filter is typically designed to reject line frequencies of 50Hz and 60Hz plus their harmonics. The filter rejection performance is directly related to the accuracy of the converter system clock. The LTC2483 incorporates a highly accurate on-chip oscillator. This eliminates the need for external frequency setting components such as crystals or oscillators.
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LTC2483
APPLICATIO S I FOR ATIO
Frequency Rejection Selection (CA0/F0)
The LTC2483 internal oscillator provides better than 87dB normal mode rejection at line frequencies of 50Hz and 60Hz and all of their harmonics (up to the 255th) from 48Hz to 62.4Hz. When a fundamental rejection frequency different from 50Hz/60Hz is required or when the converter must be synchronized with an outside source, the LTC2483 can operate with an external conversion clock. The converter
1...7
8
9
1
7-BIT ADDRESS START BY MASTER SLEEP
R ACK BY LTC2483
SGN
Figure 3. Timing Diagram for Reading from the LTC2483
S
7-BIT ADDRESS
R/W
ACK
SLEEP
Figure 4. The LTC2483 Conversion Sequence
S
7-BIT ADDRESS
R ACK
READ
CONVERSION
SLEEP
DATA OUTPUT
Figure 5. Consecutive Reading at the Same Configuration
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automatically detects the presence of an external clock signal at the CA0/F0 pin and turns off the internal oscillator. The chip address for CA0 is internally set HIGH. The frequency fEOSC of the external signal must be at least 10kHz to be detected. The external clock signal duty cycle is not significant as long as the minimum and maximum specifications for the high and low periods tHEO and tLEO are observed. While operating with an external conversion clock of a frequency fEOSC, the LTC2483 provides better than 110dB
2... 9 1 2 3 4 5 6 7 8 9 MSB D15 ACK BY MASTER DATA OUTPUT
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LSB NAK BY MASTER
DATA
Sr
DATA TRANSFERRING
P CONVERSION
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DATA INPUT/OUTPUT
P
S CONVERSION
7-BIT ADDRESS
R ACK
READ
P
SLEEP
DATA OUTPUT
CONVERSION
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APPLICATIO S I FOR ATIO
normal mode rejection in a frequency range of fEOSC/5120 4% and its harmonics. The normal mode rejection as a function of the input frequency deviation from fEOSC/5120 is shown in Figure 6.
-80 -85
NORMAL MODE REJECTION (dB)
-90 -95 -100 -105 -110 -115 -120 -125 -130 -135 -140 -12 -8 -4 0 4 8 12 DIFFERENTIAL INPUT SIGNAL FREQUENCY DEVIATION FROM NOTCH FREQUENCY fEOSC/5120(%)
2483 F06
Figure 6. LTC2483 Normal Mode Rejection When Using an External Oscillator
Whenever an external clock is not present at the CA0/F0 pin, the converter automatically activates its internal oscillator and enters the Internal Conversion Clock mode. CA0/F0 may be tied HIGH or left floating in order to set the chip address. The LTC2483 operation will not be disturbed if the change of conversion clock source occurs during the sleep state or during the data output state while the converter uses an external serial clock. If the change occurs during the conversion state, the result of the conversion in progress may be outside specifications but the following conversions will not be affected. Table 4 summarizes the duration of the conversion state of each state and the achievable output data rate as a function of fEOSC.
Table 4. LTC2483 State Duration
STATE CONVERSION OPERATING MODE Internal Oscillator External Oscillator 50Hz/60Hz Rejection
CA0/F0 = External Oscillator with Frequency fEOSC Hz (fEOSC/5120 Rejection)
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Ease of Use The LTC2483 data output has no latency, filter settling delay or redundant data associated with the conversion cycle. There is a one-to-one correspondence between the conversion and the output data. Therefore, multiplexing multiple analog voltages is easy. The LTC2483 performs offset and full-scale calibrations every conversion cycle. This calibration is transparent to the user and has no effect on the cyclic operation described above. The advantage of continuous calibration is extreme stability of offset and full-scale readings with respect to time, supply voltage change and temperature drift. Power-Up Sequence The LTC2483 automatically enters an internal reset state when the power supply voltage VCC drops below approximately 2V. This feature guarantees the integrity of the conversion result. When the VCC voltage rises above this critical threshold, the converter creates an internal power-on-reset (POR) signal with a duration of approximately 4ms. The POR signal clears all internal registers. Following the POR signal, the LTC2483 starts a normal conversion cycle and follows the succession of states described in Figure 1. The first conversion result following POR is accurate within the specifications of the device if the power supply voltage is restored within the operating range (2.7V to 5.5V) before the end of the POR time interval. Reference Voltage Range The LTC2483 external reference voltage range is 0.1V to VCC. The converter output noise is determined by the
DURATION 147ms, Output Data Rate 6.8 Readings/s 41036/fEOSCs, Output Data Rate fEOSC/41036 Readings/s
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thermal noise of the front-end circuits, and as such, its value in nanovolts is nearly constant with reference voltage. Since the transition noise (600nV) is much less than the quantization noise (VREF/217), a decrease in the reference voltage will increase the converter resolution. A reduced reference voltage will also improve the converter performance when operated with an external conversion clock (external FO signal) at substantially higher output data rates (see the Output Data Rate section). The reference input is differential. The differential reference input range (VREF = REF+ - REF-) is 100mV to VCC and the common mode reference input range is 0V to VCC. Input Voltage Range The analog input is truly differential with an absolute/ common mode range for the IN+ and IN- input pins extending from GND - 0.3V to VCC + 0.3V. Outside these limits, the ESD protection devices begin to turn on and the errors due to input leakage current increase rapidly. Within these limits, the LTC2483 converts the bipolar differential input signal, VIN = IN+ - IN-, from - FS to +FS where FS = 0.5 * VREF. Beyond this range, the converter indicates the overrange or the underrange condition using distinct output codes. Since the differential input current cancellation does not rely on an on-chip buffer, current cancellation and DC performance is maintained rail-to-rail.
IREF+ VREF + ILEAK IIN+ VIN+ ILEAK IIN- VIN- ILEAK IREF- VREF- ILEAK SWITCHING FREQUENCY fSW = 123kHz INTERNAL OSCILLATOR fSW = 0.4 * fEOSC EXTERNAL OSCILLATOR VCC ILEAK RSW (TYP) 10k
2483 F07
VCC ILEAK RSW (TYP) 10k
I IN+ VCC ILEAK RSW (TYP) 10k CEQ 12pF (TYP) RSW (TYP) 10k
I REF +
VCC ILEAK
REQ = 2.98M INTERNAL OSCILLATOR REQ = 0.833 * 1012 / f EOSC EXTERNAL OSCILLATOR DT IS THE DENSITY OF A DIGITAL TRANSITION AT THE MODULATOR OUTPUT WHERE REF- IS INTERNALLY TIED TO GND
Figure 7. LTC2483 Equivalent Analog Input Circuit
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Input signals applied to IN+ and IN- pins may extend by 300mV below ground and above VCC. In order to limit any fault current, resistors of up to 5k may be added in series with the IN+ and IN- pins without affecting the performance of the devices. The effect of the series resistance on the converter accuracy can be evaluated from the curves presented in the Input Current/Reference Current sections. In addition, series resistors will introduce a temperature dependent offset error due to the input leakage current. A 1nA input leakage current will develop a 1ppm offset error on a 5k resistor if VREF = 5V. This error has a very strong temperature dependency. Driving the Input and Reference The input and reference pins of the LTC2483 converter are directly connected to a network of sampling capacitors. Depending upon the relation between the differential input voltage and the differential reference voltage, these capacitors are switching between these four pins transferring small amounts of charge in the process. A simplified equivalent circuit is shown in Figure 7. For a simple approximation, the source impedance RS driving an analog input pin (IN+, IN-, REF+ or REF-) can be considered to form, together with RSW and CEQ (see Figure 7), a first order passive network with a time constant = (RS + RSW) * CEQ. The converter is able to sample the
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()
AVG
= I IN - =
()
AVG
=
VIN(CM) - VREF(CM) 0.5 * REQ
()
AVG
2 VIN 2 1.5 * VREF - VINCM + VREFCM 0.5 * VREF * DT 1.5VREF + VREF(CM) - VIN(CM) VIN - - - 0.5 * REQ 0.5 * REQ VREF * REQ REQ VREF * REQ
(
)
where: REF + + REF - + - VREFCM = , VREF = REF - REF 2 VIN = IN+ - IN- IN+ + IN- VINCM = 2
(
)
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APPLICATIO S I FOR ATIO
input signal with better than 1ppm accuracy if the sampling period is at least 14 times greater than the input circuit time constant . The sampling process on the four input analog pins is quasi-independent so each time constant should be considered by itself and, under worst-case circumstances, the errors may add. When using the internal oscillator, the LTC2483's frontend switched-capacitor network is clocked at 123kHz corresponding to an 8.1s sampling period. Thus, for settling errors of less than 1ppm, the driving source impedance should be chosen such that 8.1s/14 = 580ns. When an external oscillator of frequency fEOSC is used, the sampling period is 2.5/fEOSC and, for a settling error of less than 1ppm, 0.178/fEOSC. Automatic Differential Input Current Cancellation In applications where the sensor output impedance is low (up to 10k with no external bypass capacitor or up to 500 with 0.001F bypass), complete settling of the input occurs. In this case, no errors are introduced and direct digitization of the sensor is possible. For many applications, the sensor output impedance combined with external bypass capacitors produces RC time constants much greater than the 580ns required for 1ppm accuracy. For example, a 10k bridge driving a 0.1F bypass capacitor has a time constant an order of magnitude greater than the required maximum. Historically, settling issues were solved using buffers. These buffers led to increased noise, reduced DC performance (Offset/ Drift), limited input/output swing (cannot digitize signals near ground or VCC), added system cost and increased power. The LTC2483 uses a proprietary switching algorithm that forces the average differential input current to zero independent of external settling errors. This allows accurate direct digitization of high impedance sensors without the need of buffers (see Figures 8 to 10). Additional errors resulting from mismatched leakage currents must also be taken into account. The switching algorithm forces the average input current on the positive input (IIN+) to be equal to the average input current on the negative input (IIN-). Over the complete conversion cycle, the average differential input current (IIN+ - IIN-) is zero. While the differential input current is
+FS ERROR (ppm)
-FS ERROR (ppm)
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RSOURCE CPAR 20pF LTC2483 RSOURCE CPAR 20pF IN + CEXT VINCM + 0.5VIN IN - CEXT
2483 F08
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VINCM - 0.5VIN
Figure 8. An RC Network at IN+ and IN-
VCC = 5V 60 VREF = 5V VIN+ = 3.75V - 40 VIN = 1.25V TA = 25C
80
CEXT = 0pF CEXT = 100pF CEXT = 1nF, 0.1F, 1F
20 0 -20 -40 -60 -80 1
10
100 1k RSOURCE ()
10k
100k
2483 F09
Figure 9. +FS Error vs RSOURCE at IN+ and IN-
VCC = 5V 60 VREF = 5V VIN+ = 1.25V - 40 VIN = 3.75V TA = 25C 20 0 -20 -40 -60 -80 1 10
80
CEXT = 1nF, 0.1F, 1F
CEXT = 100pF CEXT = 0pF
100 1k RSOURCE ()
10k
100k
2483 F10
Figure 10. -FS Error vs RSOURCE at IN+ and IN-
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zero, the common mode input current (IIN++ IIN-)/2 is proportional to the difference between the common mode input voltage (VINCM) and the common mode reference voltage (VREFCM). In applications where the input common mode voltage is equal to the reference common mode voltage, as in the case of a balance bridge type application, both the differential and common mode input current are zero. The accuracy of the converter is unaffected by settling errors. Mismatches in source impedances between IN+ and IN- also do not affect the accuracy. In applications where the input common mode voltage is constant but different from the reference common mode voltage, the differential input current remains zero while the common mode input current is proportional to the difference between VINCM and VREFCM. For a reference common mode of 2.5V and an input common mode of 1.5V, the common mode input current is approximately 0.74A. This common mode input current has no effect on the accuracy if the external source impedances tied to IN+ and IN- are matched. Mismatches in these source impedances lead to a fixed offset error but do not affect the linearity or full-scale reading. A 1% mismatch in 1k source resistances leads to a 15ppm shift (74V) in offset voltage. In applications where the common mode input voltage varies as a function of input signal level (single-ended input, RTDs, half bridges, current sensors, etc.), the common mode input current varies proportionally with input voltage. For the case of balanced input impedances, the common mode input current effects are rejected by the large CMRR of the LTC2483 leading to little degradation in accuracy. Mismatches in source impedances lead to gain errors proportional to the difference between the common mode input voltage and the common mode reference voltage. 1% mismatches in 1k source resistances lead to worst-case gain errors on the order of 15ppm or 1LSB (for 1V differences in reference and input common mode voltage). Table 5 summarizes the effects of mismatched source impedance and differences in reference/input common mode voltages.
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Table 5. Suggested Input Configuration for LTC2483
BALANCED INPUT RESISTANCES Constant VIN(CM) - VREF(CM) CEXT > 1nF at Both IN+ and IN-. Can Take Large Source Resistance with Negligible Error UNBALANCED INPUT RESISTANCES CEXT > 1nF at Both IN+ and IN-. Can Take Large Source Resistance. Unbalanced Resistance Results in an Offset Which Can be Calibrated Minimize IN+ and IN- Capacitors and Avoid Large Source Impedance (< 5k Recommended) Varying VIN(CM) - VREF(CM) CEXT > 1nF at Both IN+ and IN-. Can Take Large Source Resistance with Negligible Error
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The magnitude of the dynamic input current depends upon the size of the very stable internal sampling capacitors and upon the accuracy of the converter sampling clock. The accuracy of the internal clock over the entire temperature and power supply range is typically better than 0.5%. Such a specification can also be easily achieved by an external clock. When relatively stable resistors (50ppm/C) are used for the external source impedance seen by IN+ and IN-, the expected drift of the dynamic current and offset will be insignificant (about 1% of their respective values over the entire temperature and voltage range). Even for the most stringent applications, a one-time calibration operation may be sufficient. In addition to the input sampling charge, the input ESD protection diodes have a temperature dependent leakage current. This current, nominally 1nA (10nA max), results in a small offset shift. A 1k source resistance will create a 1V typical and 10V maximum offset voltage. Reference Current In a similar fashion, the LTC2483 samples the differential reference pins REF+ and REF- transferring small amount of charge to and from the external driving circuits thus producing a dynamic reference current. This current does not change the converter offset, but it may degrade the gain and INL performance. The effect of this current can be analyzed in two distinct situations. For relatively small values of the external reference capacitors (CREF < 1nF), the voltage on the sampling capacitor settles almost completely and relatively large values for the source impedance result in only small errors. Such values for CREF will deteriorate the converter offset and gain
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performance without significant benefits of reference filtering and the user is advised to avoid them. Larger values of reference capacitors (CREF > 1nF) may be required as reference filters in certain configurations. Such capacitors will average the reference sampling charge and the external source resistance will see a quasi constant reference differential impedance. In the following discussion, it is assumed the input and reference common mode are the same. For the internal oscillator, the related difference resistance is 1.1M and
90 80 70
+FS ERROR (ppm)
-FS ERROR (ppm)
60 50 40 30 20 10 0 -10 0
VCC = 5V VREF = 5V VIN+ = 3.75V VIN- = 1.25V TA = 25C CREF = 0.01F CREF = 0.001F CREF = 100pF CREF = 0pF
10
1k 100 RSOURCE ()
10k
100k
2483 F11
Figure 11. +FS Error vs RSOURCE at REF+ or REF- (Small CREF)
500
400
+FS ERROR (ppm)
300
CREF = 0.1F
-FS ERROR (ppm)
VCC = 5V VREF = 5V VIN+ = 3.75V VIN- = 1.25V TA = 25C
CREF = 1F, 10F
-100
200 CREF = 0.01F 100
0
0
200
600 400 RSOURCE ()
800
1000
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Figure 13. +FS Error vs RSOURCE
at REF+
or REF-
(Large CREF)
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the resulting full-scale error is 0.46ppm for each ohm of source resistance driving the REF+ and REF- pins. When CA0/F0 is driven by an external oscillator with a frequency fEOSC (external conversion clock operation), the typical differential reference resistance is 0.30 * 1012/fEOSC and each ohm of source resistance driving the REF+ or REF- pins will result in 1.67 * 10-6 * fEOSCppm gain error. The typical +FS and -FS errors for various combinations of source resistance seen by the REF+ or REF- pins and external capacitance connected to that pin are shown in Figures 11-14.
10 0 -10 -20 -30 -40 -50 -60 VCC = 5V VREF = 5V -70 V + = 1.25V IN - -80 VIN = 3.75V TA = 25C -90 10 0
CREF = 0.01F CREF = 0.001F CREF = 100pF CREF = 0pF
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1k 100 RSOURCE ()
10k
100k
2483 F12
Figure 12. -FS Error vs RSOURCE at REF+ or REF- (Small CREF)
0
CREF = 0.01F
-200
CREF = 1F, 10F
-300
-400
-500
VCC = 5V VREF = 5V VIN+ = 1.25V VIN- = 3.75V TA = 25C
0
CREF = 0.1F
200
600 400 RSOURCE ()
800
1000
2483 F14
Figure 14. -FS Error vs RSOURCE
at REF+ or REF- (Large C
REF)
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In addition to this gain error, the converter INL performance is degraded by the reference source impedance. The INL is caused by the input dependent terms -VIN2/(VREF * REQ) - (0.5 * VREF * DT)/REQ in the reference pin current as expressed in Figure 7. When using internal oscillator, every 100 of reference source resistance translates into about 0.61ppm additional INL error. When CA0/F0 is driven by an external oscillator with a frequency fEOSC, every 100 of source resistance driving REF+ or REF- translates into about 2.18 * 10-6 * fEOSCppm additional INL error. Figure 15 shows the typical INL error due to the source resistance driving the REF+ or REF- pins when large CREF values are used. The user is advised to minimize the source impedance driving the REF+ and REF- pins. In applications where the reference and input common mode voltages are different, extra errors are introduced. For every 1V of the reference and input common mode voltage difference (VREFCM - VINCM) and a 5V reference, each Ohm of reference source resistance introduces an extra (VREFCM - VINCM)/(VREF * REQ) full-scale gain error, which is 0.067ppm when using internal oscillator. If an
10
INL (ppm OF VREF)
VCC = 5V 8 VREF = 5V VIN(CM) = 2.5V 6 T = 25C A 4 CREF = 10F 2 0
-2 -4 -6 -8 -10 - 0.5 - 0.3 0.1 - 0.1 VIN/VREF (V)
Figure 15. INL vs DIFFERENTIAL Input Voltage and Reference Source Resistance for CREF > 1F
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external clock is used, the corresponding extra gain error is 0.24 * 10-6 * fEOSCppm. The magnitude of the dynamic reference current depends upon the size of the very stable internal sampling capacitors and upon the accuracy of the converter sampling clock. The accuracy of the internal clock over the entire temperature and power supply range is typically better than 0.5%. Such a specification can also be easily achieved by an external clock. When relatively stable resistors (50ppm/C) are used for the external source impedance seen by REF+ and REF-, the expected drift of the dynamic current gain error will be insignificant (about 1% of its value over the entire temperature and voltage range). Even for the most stringent applications a one-time calibration operation may be sufficient. In addition to the reference sampling charge, the reference pins ESD protection diodes have a temperature dependent leakage current. This leakage current, nominally 1nA (10nA max), results in a small gain error. A 100 source resistance will create a 0.05V typical and 0.5V maximum full-scale error.
R = 1k R = 500 R = 100 0.3 0.5
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Output Data Rate When using its internal oscillator, the LTC2483 produces up to 6.82sps with simultaneous 50Hz/60Hz rejection. The actual output data rate will depend upon the length of the sleep and data output phases which are controlled by the user and which can be made insignificantly short. When operated with an external conversion clock (CA0/F0 connected to an external oscillator), the LTC2483 output data rate can be increased as desired. The duration of the conversion phase is 41036/fEOSC. If fEOSC = 307.2kHz, the converter notch is set at 60Hz. An increase in fEOSC over the nominal 307.2kHz will translate into a proportional increase in the maximum
50 40 30 TA = 85C 20 10 0 TA = 25C -10 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC)
2483 F16
OFFSET ERROR (ppm OF VREF)
+FS ERROR (ppm OF VREF)
VIN(CM) = VREF(CM) VCC = VREF = 5V VIN = 0V CA0/F0 = EXT CLOCK
Figure 16. Offset Error vs Output Data Rate and Temperature
0 -500
-FS ERROR (ppm OF VREF)
TA = 25C TA = 85C -2000
-1500
RESOLUTION (BITS)
-1000
-2500 -3000 VIN(CM) = VREF(CM) VCC = VREF = 5V CA0/F0 = EXT CLOCK 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC)
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-3500
Figure 18. -FS Error vs Output Data Rate and Temperature
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output data rate. The increase in output rate is nevertheless accompanied by three potential effects, which must be carefully considered. First, a change in fEOSC will result in a proportional change in the internal notch position and in a reduction of the converter differential mode rejection at the power line frequency. In many applications, the subsequent performance degradation can be substantially reduced by relying upon the LTC2483's exceptional common mode rejection and by carefully eliminating common mode to differential mode conversion sources in the input circuit. The user should avoid single-ended input filters and should maintain a very high degree of matching and symmetry in the circuits driving the IN+ and IN- pins.
3500 3000 2500 TA = 85C 2000 1500 1000 500 0 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC)
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VIN(CM) = VREF(CM) VCC = VREF = 5V CA0/F0 = EXT CLOCK
TA = 25C
Figure 17. +FS Error vs Output Data Rate and Temperature
24 TA = 25C 22 TA = 85C 20 18 16 14 12 10 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC) VIN(CM) = VREF(CM) VCC = VREF = 5V VIN = 0V CA0/F0 = EXT CLOCK RES = LOG 2 (VREF/NOISERMS)
Figure 19. Resolution (NoiseRMS 1LSB) vs Output Data Rate and Temperature
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LTC2483
APPLICATIO S I FOR ATIO
Second, the increase in clock frequency will increase proportionally the amount of sampling charge transferred through the input and the reference pins. If large external input and/or reference capacitors (CIN, CREF) are used, the previous section provides formulae for evaluating the effect of the source resistance upon the converter performance for any value of fEOSC. If small external input and/or reference capacitors (CIN, CREF) are used, the effect of the external source resistance upon the LTC2483 typical performance can be inferred from Figures 9, 10, 11 and 12 in which the horizontal axis is scaled by 307200/fEOSC.
22 20 RESOLUTION (BITS) 18 TA = 85C 16 14 VIN(CM) = VREF(CM) 12 VCC = VREF = 5V CA0/F0 = EXT CLOCK RES = LOG 2 (VREF/INLMAX) 10 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC)
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OFFSET ERROR (ppm OF VREF)
TA = 25C
Figure 20. Resolution (INLMAX 1LSB) vs Output Data Rate and Temperature
24 VCC = VREF = 5V 22
RESOLUTION (BITS) RESOLUTION (BITS)
20 18 16
VCC = 5V, VREF = 2.5V
18 VCC = VREF = 5V 16 14 VCC = 5V, VREF = 2.5V
14 VIN(CM) = VREF(CM) VIN = 0V CA0/F0 = EXT CLOCK 12 T = 25C A RES = LOG 2 (VREF/NOISERMS) 10 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC)
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Figure 22. Resolution (NoiseRMS 1LSB) vs Output Data Rate and Reference Voltage
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Third, an increase in the frequency of the external oscillator above 1MHz (a more than 3+ increase in the output data rate) will start to decrease the effectiveness of the internal autocalibration circuits. This will result in a progressive degradation in the converter accuracy and linearity. Typical measured performance curves for output data rates up to 100 readings per second are shown in Figures 16 to 23. In order to obtain the highest possible level of accuracy from this converter at output data rates above 20 readings per second, the user is advised to maximize the power supply voltage used and to limit the maximum ambient operating temperature. In certain circumstances, a reduction of the differential reference voltage may be beneficial.
20 VIN(CM) = VREF(CM) VIN = 0V 15 CA0/F0 = EXT CLOCK TA = 25C 10 VCC = VREF = 5V 5 0 -5 VCC = 5V, VREF = 2.5V -10 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC)
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Figure 21. Offset Error vs Output Data Rate and Reference Voltage
22 20
VIN(CM) = VREF(CM) VIN = 0V 12 CA0/F0 = EXT CLOCK TA = 25C RES = LOG 2 (VREF/INLMAX) 10 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC)
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Figure 23. Resolution (INLMAX 1LSB) vs Output Data Rate and Reference Voltage
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LTC2483
APPLICATIO S I FOR ATIO
Input Bandwidth
The combined effect of the internal SINC4 digital filter and of the analog and digital autocalibration circuits determines the LTC2483 input bandwidth. When the internal oscillator is used, the 3dB input bandwidth is 3.3Hz. If an external conversion clock generator of frequency fEOSC is connected to the CA0/F0 pin, the 3dB input bandwidth is 11.8 * 10-6 * fEOSC. Due to the complex filtering and calibration algorithms utilized, the converter input bandwidth is not modeled very accurately by a first order filter with the pole located at the 3dB frequency. When the internal oscillator is used, the shape of the LTC2483 input bandwidth is shown in Figure 24. When an external oscillator of frequency fEOSC is used, the shape of the LTC2483 input bandwidth can be derived from Figure 24, in which the horizontal axis is scaled by f EOSC/279.2kHz. The conversion noise (600nVRMS typical for VREF = 5V) can be modeled by a white noise source connected to a noise free converter. The noise spectral density is 47nVHz for an infinite bandwidth source and 64nVHz for a single 0.5MHz pole source. From these numbers, it is clear that particular attention must be given to the design of external amplification circuits. Such circuits face the simultaneous requirements of very low bandwidth (just a few Hz) in order to reduce the output referred noise and relatively high bandwidth (at least 500kHz) necessary to drive the input switched-capacitor network. A possible solution is a high gain, low bandwidth amplifier stage followed by a high bandwidth unity-gain buffer. When external amplifiers are driving the LTC2483, the ADC input referred system noise calculation can be simplified by Figure 25. The noise of an amplifier driving the LTC2483 input pin can be modeled as a band limited white noise source. Its bandwidth can be approximated by the bandwidth of a single pole lowpass filter with a corner frequency fi. The amplifier noise spectral density is ni. From Figure 25, using fi as the x-axis selector, we can find on the y-axis the noise equivalent bandwidth freqi of the input driving amplifier. This bandwidth includes the band limiting effects of the ADC internal calibration and filtering. The noise of the driving amplifier referred to the converter input and including all these
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effects can be calculated as N = ni * freqi. The total system noise (referred to the LTC2483 input) can now be obtained by summing as square root of sum of squares the three ADC input referred noise sources: the LTC2483 internal noise, the noise of the IN+ driving amplifier and the noise of the IN- driving amplifier. If the CA0/F0 pin is driven by an external oscillator of frequency fEOSC, Figure 25 can still be used for noise calculation if the x-axis is scaled by fEOSC/307200. For large values of the ratio fEOSC/307200, the Figure 25 plot accuracy begins to decrease, but at the same time the LTC2483 noise floor rises and the noise contribution of the driving amplifiers lose significance. Normal Mode Rejection and Antialiasing One of the advantages delta-sigma ADCs offer over conventional ADCs is on-chip digital filtering. Combined with a large oversampling ratio, the LTC2483 significantly simplifies antialiasing filter requirements. Additionally, the input current cancellation feature of the LTC2483 allows external lowpass filtering without degrading the DC performance of the device. The SINC4 digital filter provides greater than 120dB normal mode rejection at all frequencies except DC and integer multiples of the modulator sampling frequency (fS). The LTC2483's autocalibration circuits further simplify the antialiasing requirements by additional normal mode signal filtering both in the analog and digital domain. Independent of the operating mode, fS = 256 * fN = 2048 * fOUTMAX where fN is the notch frequency and fOUTMAX is the maximum output data rate. In the internal oscillator mode, fS = 13960Hz. In the external oscillator mode, fS = fEOSC/20. The performance of the normal mode rejection is shown in Figures 26 and 27. The regions of low rejection occurring at integer multiples of fS have a very narrow bandwidth. Magnified details of the normal mode rejection curves are shown in Figure 28 (rejection near DC) and Figure 29 (rejection at fS = 256fN) where fN represents the notch frequency. These curves have been derived for the external oscillator mode but they can be used in all operating modes by appropriately selecting the fN value.
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LTC2483
APPLICATIO S I FOR ATIO
0
INPUT SIGNAL ATTENUATION (dB)
INPUT REFERRED NOISE EQUIVALENT BANDWIDTH (Hz)
-1 -2 -3 -4 -5 -6
60Hz fEOSC = 307.2kHz
50Hz fEOSC = 256kHz
INTERNAL OSCILLATOR
1 3 4 0 5 2 DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
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Figure 24. Input Signal Using the Internal Oscillator
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INPUT NORMAL MODE REJECTION (dB)
-20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 0 fS 2fS 3fS 4fS 5fS 6fS 7fS 8fS 9fS 10fS11fS12fS DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
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INPUT NORMAL MODE REJECTION (dB)
-10
Figure 26. Input Normal Mode Rejection, External Oscillator (fEOSC = 256kHz) 50Hz Rejection
0 fN = fEOSC/5120
INPUT NORMAL MODE REJECTION (dB)
-20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 0 fN 2fN 3fN 4fN 5fN 6fN 7fN INPUT SIGNAL FREQUENCY (Hz) 8fN
INPUT NORMAL MODE REJECTION (dB)
-10
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Figure 28. Input Normal Mode Rejection at DC
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100 10 1 0.1 0.1 1 10 100 1k 10k 100k 1M INPUT NOISE SOURCE SINGLE POLE EQUIVALENT BANDWIDTH (Hz) 2483 F25
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Figure 25. Input Refered Noise Equivalent Bandwidth of an Input Connected White Noise Source
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 0 fS 2fS 3fS 4fS 5fS 6fS 7fS 8fS 9fS 10fS DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
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Figure 27. Input Normal Mode Rejection at DC (Internal Oscillator)
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 250fN 252fN 254fN 256fN 258fN 260fN 262fN INPUT SIGNAL FREQUENCY (Hz)
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Figure 29. Input Normal Mode Rejection at fs = 256fN
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LTC2483
APPLICATIO S I FOR ATIO
The user can expect to achieve this level of performance using the internal oscillator as it is demonstrated by Figures 30, 31 and 32. Typical measured values of the normal mode rejection of the LTC2483 operating with an external oscillator and a 60Hz notch setting are shown in Figure 30 superimposed over the theoretical calculated curve. Similarly, the measured normal rejection of the LTC2483 for 50Hz rejection (fEOSC = 256kHz) and 50Hz/ 60Hz rejection (internal oscillator) are shown in Figures 31 and 32. As a result of these remarkable normal mode specifications, minimal (if any) antialias filtering is required in front of the LTC2483. If passive RC components are placed in front of the LTC2483, the input dynamic current should be considered (see Input Current section). In this case, the differential input current cancellation feature of the LTC2483 allows external RC networks without significant degradation in DC performance. Traditional high order delta-sigma modulators, while providing very good linearity and resolution, suffer from potential instabilities at large input signal levels. The proprietary architecture used for the LTC2483 third order modu-
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lator resolves this problem and guarantees a predictable stable behavior at input signal levels of up to 150% of full scale. In many industrial applications, it is not uncommon to have to measure microvolt level signals superimposed on volt level perturbations and the LTC2483 is eminently suited for such tasks. When the perturbation is differential, the specification of interest is the normal mode rejection for large input signal levels. With a reference voltage VREF = 5V, the LTC2483 has a full-scale differential input range of 5V peak-to-peak. Figures 33 and 34 show measurement results for the LTC2483 normal mode rejection ratio with a 7.5V peak-to-peak (150% of full scale) input signal superimposed over the more traditional normal mode rejection ratio results obtained with a 5V peak-topeak (full scale) input signal. In Figure 33, the LTC2483 uses the external oscillator with the notch set at 60Hz and in Figure 34 it uses the external oscillator with the notch set at 50Hz. It is clear that the LTC2483 rejection performance is maintained with no compromises in this extreme situation. When operating with large input signal levels, the user must observe that such signals do not violate the device absolute maximum ratings.
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LTC2483
APPLICATIO S I FOR ATIO
0
NORMAL MODE REJECTION (dB)
-20 -40 - 60 -80 -100 -120
NORMAL MODE REJECTION (dB)
MEASURED DATA CALCULATED DATA
0
15
30
45
60
75
90 105 120 135 150 165 180 195 210 225 240 INPUT FREQUENCY (Hz)
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Figure 30. Input Normal Mode Rejection vs Input Frequency with Input Perturbation of 100% Full Scale (60Hz Notch fEOSC = 307.2kHz)
0
NORMAL MODE REJECTION (dB)
NORMAL MODE REJECTION (dB)
-20 -40 - 60 -80 -100 -120
MEASURED DATA CALCULATED DATA
0
20
40
60
80 100 120 140 INPUT FREQUENCY (Hz)
160
180
Figure 32. Input Normal Mode Rejection vs Input Frequency with Input Perturbation of 100% Full Scale (Internal Oscillator)
0
NORMAL MODE REJECTION (dB)
-20 -40 - 60 -80 -100 -120
0
12.5 25 37.5 50 62.5 75 87.5 100 112.5 125 137.5 150 162.5 175 187.5 200 INPUT FREQUENCY (Hz)
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Figure 34. Measured Input Normal Mode Rejection vs Input Frequency with Input Perturbation of 150% Full Scale (50Hz Notch fEOSC = 256kHz)
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VCC = 5V VREF = 5V VIN(CM) = 2.5V VIN(P-P) = 5V TA = 25C 0 -20 -40 - 60 -80 -100 -120 MEASURED DATA CALCULATED DATA VCC = 5V VREF = 5V VIN(CM) = 2.5V VIN(P-P) = 5V TA = 25C 0 12.5 25 37.5 50 62.5 75 87.5 100 112.5 125 137.5 150 162.5 175 187.5 200 INPUT FREQUENCY (Hz)
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Figure 31. Input Normal Mode Rejection vs Input Frequency with Input Perturbation of 100% Full Scale (50Hz Notch fEOSC = 256kHz)
VCC = 5V VREF = 5V VIN(CM) = 2.5V VIN(P-P) = 5V TA = 25C
0 -20 -40 - 60 -80 -100 -120 VIN(P-P) = 5V VIN(P-P) = 7.5V (150% OF FULL SCALE)
VCC = 5V VREF = 5V VINCM = 2.5V TA = 25C
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0
15
30
45
60
75
90 105 120 135 150 165 180 195 210 225 240 INPUT FREQUENCY (Hz)
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Figure 33. Measured Input Normal Mode Rejection vs Input Frequency with Input Perturbation of 150% Full Scale (60Hz Notch fEOSC = 307.2kHz)
VCC = 5V VREF = 5V VIN(CM) = 2.5V TA = 25C
VIN(P-P) = 5V VIN(P-P) = 7.5V (150% OF FULL SCALE)
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LTC2483
APPLICATIO S I FOR ATIO
/* LTC248X.h Processor setup and Lots of useful defines for configuring the LTC2481, LTC2483, and LTC2485. */ #include <16F73.h> // Device #use delay(clock=6000000) // 6MHz clock //#fuses NOWDT,HS, PUT, NOPROTECT, NOBROWNOUT // Configuration fuses #rom 0x2007={0x3F3A} // Equivalent and more reliable fuse config. #use I2C(master, sda=PIN_C5, scl=PIN_C3, SLOW)// Set up i2c port #include "PCM73A.h" // Various defines #include "lcd.c" // LCD driver functions #define READ 0x01 #define WRITE 0x00 #define LTC248XADDR 0b01001000 // bitwise OR with address for read or write // The one and only LTC248X in this circuit, // with both address lines floating.
// Useful defines for the LTC2481 and LTC2485 - OR them together to make the // 8 bit config word. // These do NOT apply to the LTC2483. // Select gain - 1 to 256 (also depends on speed setting) // Does NOT apply to LTC2485. #define GAIN1 0b00000000 // G = 1 (SPD = 0), G = 1 #define GAIN2 0b00100000 // G = 4 (SPD = 0), G = 2 #define GAIN3 0b01000000 // G = 8 (SPD = 0), G = 4 #define GAIN4 0b01100000 // G = 16 (SPD = 0), G = 8 #define GAIN5 0b10000000 // G = 32 (SPD = 0), G = 16 #define GAIN6 0b10100000 // G = 64 (SPD = 0), G = 32 #define GAIN7 0b11000000 // G = 128 (SPD = 0), G = 64 #define GAIN8 0b11100000 // G = 256 (SPD = 0), G = 128 // Select ADC source - differential input or PTAT circuit #define VIN 0b00000000 #define PTAT 0b00001000 // Select rejection frequency - 50, 55, or 60Hz #define R50 0b00000010 #define R55 0b00000000 #define R60 0b00000100 // Select speed mode #define SLOW 0b00000000 // slow output rate with autozero #define FAST 0b00000001 // fast output rate with no autozero
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(SPD (SPD (SPD (SPD (SPD (SPD (SPD (SPD = = = = = = = = 1) 1) 1) 1) 1) 1) 1) 1)
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LTC2483
APPLICATIO S I FOR ATIO
/* LTC2483.c Basic voltmeter test program for LTC2483 Reads LTC2483, converts result to volts, and prints voltage to a 2 line by 16 character LCD display. Mark Thoren Linear Technonlgy Corporation June 23, 2005 Written for CCS PCM compiler, Version 3.182 */ #include "LTC248X.h" /*** read_LTC2483() ************************************************************ This is the funciton that actually does all the work of talking to the LTC2483. Arguments: Returns: addr - device address zero if conversion is in progress, 32 bit signed integer with lower 8 bits clear, 24 bit LTC2483 output word in the upper 24 bits. Data is left-justified for compatibility with the 24 bit LTC2485.
the i2c_xxxx() functions do the following: void i2c_start(void): generate an i2c start or repeat start condition void i2c_stop(void): generate an i2c stop condition char i2c_read(boolean): return 8 bit i2c data while generating an ack or nack boolean i2c_write(): send 8 bit i2c data and return ack or nack from slave device These functions are very compiler specific, and can use either a hardware i2c port or software emulation of an i2c port. This example uses software emulation. A good starting point when porting to other processors is to write your own i2c functions. Note that each processor has its own way of configuring the i2c port, and different compilers may or may not have built-in functions for the i2c port. When in doubt, you can always write a "bit bang" function for troubleshooting purposes. The "fourbytes" structure allows byte access to the 32 bit return value: struct fourbytes // Define structure of four consecutive bytes { // To allow byte access to a 32 bit int or float. int8 te0; // int8 te1; // The make32() function in this compiler will int8 te2; // also work, but a union of 4 bytes and a 32 bit int int8 te3; // is probably more portable. }; *******************************************************************************/ signed int32 read_LTC2483(char addr) { struct fourbytes // Define structure of four consecutive bytes { // To allow byte access to a 32 bit int or float. int8 te0; // int8 te1; // The make32() function in this compiler will int8 te2; // also work, but a union of 4 bytes and a 32 bit int int8 te3; // is probably more portable. };
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LTC2483
APPLICATIO S I FOR ATIO
union { signed int32 bits32; struct fourbytes by; } adc_code; // // // // //
adc_code.bits32 adc_code.by.te0 adc_code.by.te1 adc_code.by.te2 adc_code.by.te3
// Start communication with LTC2483: i2c_start(); if(i2c_write(addr | READ))// If no acknowledge, return zero { i2c_stop(); return 0; } adc_code.by.te3 = i2c_read(); adc_code.by.te2 = i2c_read(); adc_code.by.te1 = i2c_read(); adc_code.by.te0 = 0; i2c_stop(); return adc_code.bits32; } // End of read_LTC2483() /*** initialize() ************************************************************** Basic hardware initialization of controller and LCD, send Hello message to LCD *******************************************************************************/ void initialize(void) { // General initialization stuff. setup_adc_ports(NO_ANALOGS); setup_adc(ADC_OFF); setup_counters(RTCC_INTERNAL,RTCC_DIV_1); setup_timer_1(T1_DISABLED); setup_timer_2(T2_DISABLED,0,1); // This is the important part - configuring the SPI port setup_spi(SPI_MASTER|SPI_L_TO_H|SPI_CLK_DIV_16|SPI_SS_DISABLED); // fast SPI clock CKP = 0; // Set up clock edges - clock idles low, data changes on CKE = 1; // falling edges, valid on rising edges. lcd_init(); delay_ms(6); printf(lcd_putc, "Hello!"); delay_ms(500); } // End of initialize() // Initialize LCD // Obligatory hello message // for half a second
/*** main() ******************************************************************** Main program initializes microcontroller registers, then reads the LTC2483 repeatedly *******************************************************************************/ void main() { signed int32 x; // Integer result from LTC2481 float voltage; // Variable for floating point math int16 timeout; initialize(); // Hardware initialization while(1) { delay_ms(1); // Pace the main loop to something more than 1 ms // This is a basic error detection scheme. The LTC2483 will never take more than // 149.9ms to complete a conversion in the 55Hz // rejection mode.
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all 32 bits byte 0 byte 1 byte 2 byte 3
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LTC2483
APPLICATIO S I FOR ATIO
// If read_LTC2483() does not return non-zero within this time period, something // is wrong, such as an incorrect i2c address or bus conflict. if((x = read_LTC2483(LTC248XADDR)) != 0) { // No timeout, everything is okay timeout = 0; // reset timer x ^= 0x80000000; // Invert MSB, result is 2's complement voltage = (float) x; // convert to float voltage = voltage * 5.0 / 2147483648.0;// Multiply by Vref, divide by 2^31 lcd_putc(`\f'); // Clear screen lcd_gotoxy(1,1); // Goto home position printf(lcd_putc, "V %01.4f", voltage); // Display voltage } else { ++timeout; } if(timeout > 200) { timeout = 200; // Prevent rollover lcd_gotoxy(1,1); printf(lcd_putc, "ERROR - TIMEOUT"); delay_ms(500); } } // End of main loop } // End of main()
PACKAGE DESCRIPTIO
DD Package 10-Lead Plastic DFN (3mm x 3mm)
(Reference LTC DWG # 05-08-1698)
R = 0.115 TYP 6 0.675 0.05 0.38 0.10 10
3.50 0.05 1.65 0.05 2.15 0.05 (2 SIDES) PACKAGE OUTLINE 0.25 0.05 0.50 BSC 2.38 0.05 (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS NOTE: 1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2). CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS PIN 1 TOP MARK (SEE NOTE 6)
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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3.00 0.10 (4 SIDES) 1.65 0.10 (2 SIDES)
(DD10) DFN 1103
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5 0.200 REF 0.75 0.05 2.38 0.10 (2 SIDES)
1
0.25 0.05 0.50 BSC
0.00 - 0.05
BOTTOM VIEW--EXPOSED PAD
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SID 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
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LTC2483
TYPICAL APPLICATIO
ISOTHERMAL R2 2k 32 REF VCC LTC2483 TYPE K THERMOCOUPLE JACK (OMEGA MPJ-K-F) 5
5V 1 R6 5k 2 3
RELATED PARTS
PART NUMBER LT1236A-5 LT1460 LT1790 LTC2400 LTC2410 DESCRIPTION Precision Bandgap Reference, 5V Micropower Series Reference Micropower SOT-23 Low Dropout Reference Family 24-Bit, No Latency ADC in SO-8 24-Bit, No Latency ADC with Differential Inputs COMMENTS 0.05% Max Initial Accuracy, 5ppm/C Drift 0.075% Max Initial Accuracy, 10ppm/C Max Drift 0.05% Max Initial Accuracy, 10ppm/C Max Drift 0.3ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200A 0.8VRMS Noise, 2ppm INL 1.45VRMS Noise, 4ppm INL, Simultaneous 50Hz/60Hz Rejection (LTC2411-1) Simultaneous 50Hz/60Hz Rejection, 800nVRMS Noise Pin Compatible with the LTC2410 0.2ppm Noise, 2ppm INL, 3ppm Total Unadjusted Errors 200A 3.5kHz Output Rate, 200nV Noise, 24.6 ENOBs Pin Compatible with LTC2482/LTC2484 Pin Compatible with LTC2483/LTC2485 Pin Compatible with LTC2480/LTC2484 Pin Compatible with LTC2480/LTC2482 Pin Compatible with LTC2481/LTC2483
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LTC2411/LTC2411-1 24-Bit, No Latency ADCs with Differential Inputs in MSOP LTC2413 LTC2415/ LTC2415-1 LTC2414/LTC2418 LTC2440 LTC2480 LTC2481 LTC2482 LTC2484 LTC2485 24-Bit, No Latency ADC with Differential Inputs 24-Bit, No Latency ADCs with 15Hz Output Rate 8-/16-Channel 24-Bit, No Latency ADCs High Speed, Low Noise 24-Bit ADC 16-Bit ADC with Easy Drive Inputs, 600nV Noise, Programmable Gain, and Temperature Sensor 16-Bit ADC with Easy Drive Inputs, 600nV Noise, I2C Interface, Programmable Gain, and Temperature Sensor 16-Bit ADC with Easy Drive Inputs 24-Bit ADC with Easy Drive Inputs 24-Bit ADC with Easy Drive Inputs, I2C Interface and Temperature Sensor
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Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
FAX: (408) 434-0507 www.linear.com
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5V PIC16F73 C8 1F C7 0.1F 1.7k 1.7k 18 17 16 15 14 13 12 11 28 27 26 25 24 23 22 21 7 6 5 4 3 2 RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 RA5 RA4 RA3 RA2 RA1 RA0 VDD 20 C6 0.1F Y1 6MHz 5V 4 IN+ SCL SDA 6 7 OSC1 OSC2 9 10 R1 1 10k D1 BAT54 5V IN- 10 CA1 GND REF- CAO/FO 9 5V D7 D6 2 x 16 CHARACTER D5 LCD DISPLAY D4 (OPTREX DMC162488 EN OR SIMILAR) RW CONTRAST GND D0 D1 D2 D3 RS VCC 5V CALIBRATE 2 1 R3 10k R4 10k R5 10k 8 3 MCLR VSS VSS
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DOWN
UP
Figure 35. Voltage Measurement Circuit
LT/LWI/TP 0805 500 * PRINTED IN USA
(c) LINEAR TECHNOLOGY CORPORATION 2005

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